picture of an Intel three eighty six sixteen megahertz processor

Understanding Intel’s Processor Generations

Intel has moved from the “Tic-Tock”* architecture production model cycle to the “Process – Architecture – Optimization” cycle.

In this model, process refers to the die size fabrication process (scaled in nanometers). Intel’s current fabrication size is 14nm, since the introduction of the 5th Generation Broadwell processors. Thus, the current “process” is Broadwell.

Architecture refers to the organization of the instruction set architecture of the processor. This is the “wiring” of the transistors, or the combination of microarchitecture and instruction set architecture. New architectures often involve significant improvements to the CPU core, such as more efficient instruction decoding and issuing front ends, improved speculative execution, improved single instruction multiple data (SSE) support, larger caches, more efficient arithmetic logic units, faster floating point engines, and other significant enhancements that often greatly improve the IPC (instructions per clock) speed of the CPU.

For desktops and most mobile CPUs, the current architecture is Skylake, introduced with the 6th Generation Skylake architecture. Every processor generation since Skylake uses essentially the same architecture. As a result, the IPC (speed per MHz, per GHz, etc) performance hasn’t changed significantly since the 6th generation until today – though there have been “optimizations..”

Intel “optimizes” the same architecture with each new generation (until a new architecture is released) with either minor or significant improvements. This optimizations involve improvements to the underlying CPU architecture such as adding new features, speeding up the ram controller, increasing ram capacity, improving processor “engines” to accelerate certain tasks, etc.

For example, compared to 6th Generation Skylake, 7th Generation Kaby Lake features the same CPU core and performance per MHz but added new features including:

  • Increased clocks speeds on some CPU models
  • Faster clock speed changes (improved Intel Speed Shift technology).
  • Improved graphic score: full hardware fixed functionH EVC/VP9 (including 4K@60fps/10bit) decoding; improved hardware HEVC encoding; full hardware fixed function VP9 8bit encoding; higher GPU clock speeds for select CPUs
  • 200 series (UnionPoint) chipset on socket 1151 (Kaby Lake is compatible with 100 series chipset motherboards after a BIOS update)
  • Up to 16 PCI Express 3.0 lanes from the CPU. 24 PCI Express 3.0 lanes from PCH.
  • Support for Intel Optane Memory storage caching.
  • Support for PTWRITE instruction to write data to an Intel Processor Trace packet stream

Compared to 7th Generation Kaby Lake, 8th/9th Generation (Coffee Lake/Coffee Lake Refresh) features largely the same CPU core and performance per MHz as Skylake/Kaby Lake. New features specific to Coffee Lake include:

  • Increased core count to six cores on Corei5 and 8th generation i7 parts; Core i3 is now a quad-core brand. 9th generation i7 and i9 parts feature eight cores.
  • Increased L3 cache in accordance to the number of threads
  • Increased turbo clock speeds across i5 and i7 CPU models (increased by up to 400MHz)
  • Increased iGPU clock speeds by 50MHz and rebranded it UHD (Ultra High Definition)
  • DDR4 memory support updated for 2666 MHz (for i5, i7 and i9 parts) and 2400MHz (for i3 parts); DDR3 memory is no longer supported on LGA1151 parts, unless using with H310C chipset
  • 300 series chip set on the second revision of socket LGA1151

Names of the Generations/Optimizations of recent Intel CPUs are:

  • 5th Gen: Broadwell
    • 14 nm process improvement to 4th Gen Haswell Architecture
  • 6th Gen: Skylake
    • New architecture built on 14 nm Broadwell Process.
  • 7th Gen: Kaby Lake
    • 6th Gen Skylake Optimization.
  • 8th Gen: Coffee Lake
    • 6th Gen Skylake Optimization.
  • 9th Gen: Coffee Lake Refresh
    • 6th Gen Skylake Optimization.
  • 10th Gen: Ice Lake
    • 10nm process improvement (Cannon Lake) and new 10th Gen architecture (Ice Lake).

For the 9th Generation, the Process – Architecture – Optimization model is:

  • Process: Broadwell
  • Architecture: Skylake
  • Optimization: Coffee Lake Refresh

Cascade Lake, which will power the 2019 Mac Pro, is fundamentally another optimization of the Skylake microarchitecture; however, its a member of the 2nd Generation Intel Xeon Scalable Processors family, formerly Cascade Lake. Thus the Process – Architecture – Optimization model is:

  • Process: Broadwell
  • Architecture: Skylake
  • Optimization: Cascade Lake

Variants of this optimization are:

  • Server: Cascade Lake-SP, Cascade Lake-AP
  • Workstation: Cascade Lake-W (2019 Mac Pro)
  • Enthusiast: Cascade Lake-X

Cascade Lake enhancements include:

  • Most of the mid-range processors have more cores for the same price
  • Frequency has increased in almost all processors
  • L3 has increased in most mid-range processors
  • Faster DDR4 is supported
  • More DRAM is supported across the stack
  • Optane DRAM is supported on almost all Gold/Platinum SKUs
  • New CPU configurations optimized for specific markets
  • Speed Select Technology for Cloud Deployments
  • New ‘Cascade Lake-AP’ Platinum 9200 family up to 56 cores and 400W per socket
  • Enhanced Spectre and Meltdown Mitigations
  • New AVX-512 VNNI instructions for Emerging Workloads

Intel also announced that Cascade Lake will be their first microarchitecture to support 3D-XPoint-based memory modules and also features Deep Learning Boost instructions, though not necessarily in all variants.

Some customers may ask about a new 10th Generation Intel Processor.

Intel has released a 10th Generation Architecture (Ice Lake) and 10 nm process improvement “Cannon Lake.” 10th Gen Ice Lake-based processors are currently only available for ultra-low wattage mobile applications, and are fairly low- end.

For the 10th Generation, the Process – Architecture – Optimization model is:

  • Process: Cannon Lake (mobile only)
  • Architecture: IceLake
  • Optimization: TigerLake (future)

Ice Lake enhancements over 8th/9th generation Skylake products include:

  • On average 18% increase in IPC in comparison to 2015 Skylake running at the same frequency and memory configuration
  • L1 instruction/data cache: 32KB/48 KiB; L2 cache: 512 KiB
  • Dynamic Tuning 2.0 which allows the CPU to stay longer sustained turbo boost
  • Six new AVX-512 instruction subsets
  • Intel Deep Learning Boost, used for machine learning/artificial intelligence inference acceleration
  • 10 nm+ transistors
  • New memory controller with DDR4 3200 and LPDDR4X 3733 support
  • Integrated support for Wi-Fi 6 (802.11ax)
  • Thunderbolt 3 support


    10th Gen Ice Lake CPUs are currently available in Core i3, Core i5, and Core i7 dual-core or quad-core parts, and have base clock speeds from 700 MHz up to 1.3 GHz. Intel is yet to release the 2.3 GHz Intel Core i7-1068G7 CPU long after its official announcement.

    https://newsroom.intel.com/news/intel-launches-first-10th-gen-intel-core-processors-redefining-next-era-laptop- experiences/#gs.kedgrb


    Intel has also released a line of processors based on Cascade Lake, called the Intel Core X-Series (Cascade Lake-X). This processor family is based on Cascade Lake, and although they boast seemingly 10th-generation processor IDs, such as the Core i9-10980XE Extreme Edition, they are Broadwell/Skylake based 14nm processors.*Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). Its replacement was announced in 2016, called “Process, Architecture, Optimization”, and is similar to a tick–tock cycle, followed by an optimization phase.

    Intel® Deep Learning Boost, a new, dedicated instruction set that accelerates neural networks on the CPU for maximum responsiveness in scenarios such as automatic image enhancements, photo indexing and photorealistic effects.


Leave a Reply

Your email address will not be published. Required fields are marked *